The present disclosure relates to semiconductor device fabrication, and, more specifically, to methods of forming integrated circuit (IC) structures with self-aligned contacts to avoid shorts and reduce contact resistance.
Electronic devices, particularly integrated circuits, comprise a large number of components fabricated by layering several different materials onto a silicon wafer. In order for the components to function as an electronic device, they are selectively, electrically connected to one another. Metal lines are utilized to electrically connect components. The metal lines provide electrical connection within a layer, while vias connect different metallization and via layers. It is important that a good connection between the via and metal line exists in order to ensure that the proper amount of current is carried with minimal resistance between the connected components.
Integrated circuit (IC) structures have internal contacts that connect the semiconductor devices to various metal levels. For example, a field effect transistor (FET) can have a gate contact and source/drain contacts. The gate contact can extend vertically through interlayer dielectric (ILD) material from a metal wire or via in the first metal level to the gate of the FET. The source/drain contacts can extend vertically through ILD material from metal wires or vias in the metal level to metal plugs or other contacts, which are on the source/drain regions of the FET. Historically, in order to avoid shorts between the gate contact and the metal plugs, the gate contact is formed on a portion of the gate that is offset from the active region of the FET and, more particularly, on a portion of the gate that extends laterally over the adjacent isolation region. However, given the ever present need for size scaling of devices, it would be advantageous to provide a method that, not only allows for a gate contact to be formed on a portion of the gate directly above the active region or close thereto, but ensures that the risk of a short developing between the gate contact and any of the metal plugs is avoided (or at least significantly reduced).
Advancing technology continues to make smaller structures in integrated circuit (IC) devices. However, as IC components get smaller, the risk of small or misaligned vias gives rise to high contact resistance or open circuits. Micro-trenching in the circuit structure can lead to poor barrier coverage and voids, which also cause high via resistance and reliability concern. In design and fabrication of smaller and smaller IC components there is an ongoing struggle between performance and reliability. That is, reliability requires thick dielectric barriers while performance requires the thinnest barrier possible.
Fabrication of integrated circuits generally requires the formation of multiple integrated circuit patterns on one or more layers over a substrate wafer. These patterns generally include numerous regions of micro-structures or nano-structures that are formed through photolithography. Photolithography is a commonly used technique in the manufacture of semiconductor devices. The process uses patterns to define regions on a substrate. More specifically, with photolithography, a photoresist layer may be formed on a substrate, such as a silicon wafer, and then the resist layer is covered with a mask containing a pattern. The mask is exposed to radiation, such as ultraviolet light (UV), which is transmitted through transparent areas of the mask to cause a chemical reaction in corresponding regions of the photoresist. In other words, in the course of processing integrated circuits and the like in semiconductor devices, a standard sequence may involve putting down a layer of material, depositing a layer of photoresist on the layer of material, patterning the photoresist by projecting a pattern on it, and developing the resist to produce a pattern of open areas that expose the underlying material, with the other areas of the material still covered by the resist. Depending on whether a positive or negative tone resist is used, the exposed or unexposed portions of the photoresist layer are removed. The portions not protected by the photoresist are then etched to form the features in the substrate.